Conventional CMOS semiconductor devices, such as the n-channel ETOX cell, are often fabricated by a twin-well process or a triple-well process. As seen in FIG. 1, the triple-well process can provide a parasitic vertical pnp 101 bipolar transistor as well as a parasitic vertical npn 103 bipolar transistor. These transistors are typically used for crucial circuit applications (e.g. voltage reference) in CMOS VLSI. The n+ and p+ source and drain structures can serve as the n+ and p+ emitters. The p-well and n-well can act as the bases and the deep n-well and p+ substrate as collectors. These bipolar transistors are in "common collector" or "emitter-up" configuration.
These vertical bipolar transistors of the prior art have several limitations.
First, they share the same p-substrate or deep n-well as their collectors and therefore can only be configured in "common collector" mode. Second, the bipolar amplification of the pnp 101 and npn 103 are typically less than three in modern CMOS technology (i.e. 0.35 .mu.m and below) due to the limitation of the well depth (as base width) and a retrograded well doping profile (desirable in advanced CMOS process for suppressing latch-up).
The vertical bipolar transistors 101 and 103 are often used to form current sources. FIGS. 3A and 3B show prior art current sources, with FIG. 2A showing a current source 301 using two npn transistors 303a and 303b and FIG. 3B showing a current source 351 using two pnp transistors 353a and 353b. The output current I.sub.o can be designed to be proportional to the reference current I.sub.ref by adjusting the ratio of the emitter areas of the transistors. For example, in FIG. 3A, the following relationship can be stated:
I.sub.o.apprxeq.I.sub.ref [A.sub.e2 /A.sub.e1 ]
where A.sub.e2 is the area of the emitter of transistor 303b and A.sub.e1 is the area of the emitter of transistor 303a.
Similarly, in FIG. 3B, the following relationship can be stated: EQU I.sub.o.apprxeq.I.sub.ref [A.sub.e2 /A.sub.e1 ]
where A.sub.e2 is the area of the emitter of transistor 353b and A.sub.e1 is the area of the emitter of transistor 353a.
The conventional designs of FIG. 3A and 3B are relatively large because of the interconnections required. Thus, what is needed is a new design for a current source that overcomes the disadvantages of the prior art and provides other advantages.